# DSP Trick: Complex Downconverters for Signals at Fs/4 or 3Fs/4

**Name:** Complex downconverters for signals at Fs/4 or 3Fs/4

**Category:** Hardware architecture

**Application:** Use for QAM modem receivers in FPGAs. Don't use if the
local oscillator needs to be frequency agile.

**Advantages:** This trick produces a trivially simple fixed frequency
complex downconverter without needing an NCO or sine lookup tables

**Introduction:**

"Classical" modem receiver architecture using complex baseband processing:

passband +---+ +---------+ signal in | | | FIR | (baseband) >----+-------->| X |----------->| Lowpass |---> real | | | | Filter | output | +---+ +---------+ I | ^ | | Cosine | +------+ | | | | +---+ +---------+ | | | | | FIR | (baseband) +----|--->| X |----------->| Lowpass |---> imaginary | | | | Filter | output | +---+ +---------+ Q | ^ +------------+ | Sine | Quadrature | | | Local |---+ | Oscillator | +------------+

The 'X' are multipliers.

[ Typically, the FIR lowpass filters will be decimating types if the signal bandwidth is much less than the sample frequency, Fs. Polyphase filters may also be used here to resample the signals at the symbol rate (or 2x the symbol rate, etc) if this is not an integer submultiple of Fs. ]

**The Trick:**

If the local oscillator isn't required to have a controllable frequency or phase, and it is possible to centre the input signal around Fs/4 or 3Fs/4, then the hardware can be dramatically simplified.

Local oscillator outputs at Fs/4:

Cos: +1, 0, -1, 0, +1, 0, -1, etc.

Sin: 0, +1, 0, -1, 0, +1, 0,

- Since we only need to multiply by 0, -1 or +1, the multiplier is trivial.
- Every second input to each filter is 0, so the filters only need to run at Fs/2. (In this case, we only need to multiply by -1 or +1.)
- The multiplier can be removed altogether, and the +/- performed in the filter, either by twiddling the coefficients or by telling the accumulator to subtract.
- Since the Cos and Sin terms are never non-zero at the same time, it may be possible to to use just one FIR filter, designed to handle I/Q interleaved data. This filter will have two accumulators which alternate between input samples.

passband +---------+ signal in | FIR |---> real baseband output I >------------->| Lowpass | | Filter |---> imaginary baseband output Q +---------+

There are filter chips designed to do this, such as the HSP43168 from Harris. (Although there are better chips for new designs...) This trick also potentially saves routing in FPGAs.

Note: if this is a QAM receiver, then a separate carrier phase correction stage after the lowpass filters will be required. Also, any frequency errors in the input signal will be present during filtering. The solution is to:

- Tolerate this problem (after quantifying its effects).
- Use an AFC loop which controls the frequency error before downconversion.
- Don't use this trick - use an NCO as the LO.

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